1. Field of the Invention
The present invention relates to a semiconductor memory device having the forced fail function of forcing a memory cell at a specified address to fail when the memory cell is accessed and to a method for testing the same.
2. Background Art
With the progression of the technology of implementing finer design rules, the development of large-capacity general-purpose semiconductor memory devices having a gigabit-level memory space and high-functionality system LSIs having a large-capacity memory macro is being pursued at a feverish space at present. In light of such a situation, a technique of producing a fail bit map, which visually shows a case where failure occurs in memory cells accessed at the time of an analysis of these semiconductor memory devices, is thought to be very important.
The technique of producing the fail bit map will be described below.
Generally, a plurality of memory cells are arranged in matrix form in a memory space on a semiconductor memory device and each memory cell is given an address represented by a row address and a column address. The fail bit map is produced based on fail address information outputted from test equipment at the time of a test on a semiconductor memory device and visually indicates the location of the fail memory cells by reproducing the matrix arrangement of the memory cells on the actual semiconductor memory device on the screen of the test equipment or by printing out such an arrangement.
To obtain the fail bit map, as a matter of course, there is a necessity to prepare a fail bit map program in advance. That is, there is a necessity to grasp the tendency of address information outputted from test equipment and the position of the memory cells given by the address information from test programs, circuit configurations, layout configurations, and so on and to store the tendency in the form of a program. With a method for checking the correctness of a fail bit map program produced and of a fail bit map obtained, the reliability of the fail bit map has been ensured by checking that the positions of failure bits are indicated correctly on the fail bit map after the intentional production of the failure bits through the working of specified memory cells on a real chip using FIB (focus ion beam) or the like.
A conventional method for checking a fail bit map will be described with reference to FIGS. 28 and 29. FIG. 28 is an explanatory drawing of part of a memory macro placed on an actual semiconductor memory device. In FIG. 28, reference numeral 11A denotes part of a memory array, reference numeral 12A denotes part of a row decoder, and reference numeral 13A denotes part of a column decoder. In the part 11A of the memory array, a plurality of memory cells having addresses are arranged in matrix form. The memory cell at the circled address of “0A” is the memory cell which has been worked intentionally by the method of FIB or the like to make a failure bit used for the checking of a fail bit map. The location of the memory cell at the address of “0A” in the part 11A of the memory array is represented by a column address of “2” and a row address of “1”. The physical order of the memory cell is represented by the third column from the left and the second row from the bottom. A test on the semiconductor memory device confirms that there has been no failure bit before the memory cell at the address of “0A” is intentionally worked for the purpose of producing the failure bit.
FIG. 29 is a fail bit map of the semiconductor memory device shown in FIG. 28. This fail bit map is represented as a matrix with 8 rows and 8 columns and reproduces the arrangement of the memory array on the real semiconductor memory device. Addresses of “0” to “7” are provided in both row and column directions and it is shown that a memory cell at solidly shaded position is defective. In this case, the memory cell at the position represented by the column address of “2” and the row address of “1” is shaded solidly; therefore, this position corresponds to that of the memory cell intentionally worked on the real semiconductor memory device to produce the failure bit.
Up to now, the reliability of the fail bit map has been ensured by using such a method.
Techniques related to the production of the fail bit map are disclosed in JP-A Nos. 2002-269996 and 2002-305223.
However, in such conventional methods for checking the fail bit maps, additional working such as FIB is required, much time is taken, and checkable address areas are limited, so that the checking of the correct indication of the entire address spaces has not been done actually.